The present invention relates generally to integrated circuit memory devices and, more particularly, to an improved jam latch for latching memory array output data.
As will be appreciated by those skilled in the art, in a domino Static Random Access Memory (SRAM), the individual cells do not employ sense amplifiers to sense the differential voltage on the bit line pairs coupled to the cross-coupled inverters that store the data. Rather, for a domino SRAM, the local bit line is precharged, discharged, and the discharge is detected. The local bit line, the means to precharge the local bit line, and the detector define a dynamic node of the domino SRAM.
A jam latch or keeper latch is used to capture data output from a memory array, such as in a domino SRAM. The jam latch temporarily holds the data so that a subsequent device or circuit can read the data. In this manner, the data may be accurately captured for a subsequent circuit stage to use the correct data level. More specifically, the jam latch performs a same cycle reset-then-set operation on the memory array output node.
In a p-domino type circuit topology, the output node is precharged to a logic low or “0” state, in which a single NFET (n-type field effect transistor) device is used to reset the latch against (1) the latch's own feedback and (2) late arriving dynamic data that is still active from a previous cycle. Where data to be read from the array (or write data to be presented at the output) is a logic high or “1” state, a PFET (p-type field effect transistor device pulls the output node up to the logic “1” state where it is held by the jam latch prior to the next reset operation. However, such reset/set fight creates a potential power burn collision in the latch, making it more difficult for a reset to occur.